1. Field of the Invention
The present invention relates to a frequency converter, and more particularly, to a frequency converter for converting input data sampled at a first frequency into output data compatible with a system operating at a second frequency.
2. Description of the Prior Art
Generally, when a television system converts an analog TV signal into a digital signal using a predetermined sampling frequency, the predetermined sampling frequency may be incompatible with a television using a different sampling frequency. Therefore, a frequency converter is required when signals sampled at one sampling frequency must be converted into signals compatible at another sampling frequency. Thus, a frequency converter allows for signals to be transmitted to systems using different sampling frequencies.
A prior art frequency converter, as disclosed by Takahashi U.S. Pat. No. 4,630,034, is illustrated in FIG. 1.
The prior art frequency converter includes a write address counter 10, a master counter 12, a memory controller 14, a read address counter 16, a first buffer memory 18, a second buffer memory 20, an interpolation controller 22, and an interpolation filter 24.
The write address counter 10 outputs a write address signal (WA) based on a count value from counting a sampling pulse signal (S.sub.A) sampled at a first sampling frequency (f.sub.A). The write address counter 10 outputs the write address signal (WA) to both the first buffer memory 18 and the second buffer memory 20.
The master counter 12 counts a sampling pulse signal (S.sub.B) sampled at a second sampling frequency (f.sub.B). The master counter 12 outputs a count value of the sampling pulse signal (S.sub.B) to the memory controller 14 and to the interpolation controller 22. The memory controller 14 receives the count value from the master counter 12 and the sampling pulse signal (S.sub.B). Based on the output from the master counter 12 and the sampling pulse signal (S.sub.B) the memory controller 14 outputs read/write control signals (R/W) to the two control lines that are connected to the first buffer memory 18 and to the second buffer memory 20, respectively.
The memory controller 14 also outputs a clear signal (CLEAR) to the write address counter 10, the master counter 12, and the read address counter 16 and outputs a control signal to the read address counter 16. Based on the received clear signal (CLEAR) and the control signal from the memory controller 14, the read address counter 16 outputs a read address signal (RA) to the first buffer memory 18 and to the second buffer memory 20. The write address counter 10 also outputs the write address signal (WA) based on the clear signal (CLEAR) from the memory controller 14.
The first and second buffer memories 18 and 20 store input data (INPUT) sampled at the sampling frequency (f.sub.A) in a memory cell based on the (R/W) control signals from the memory controller 14 and the write address signal (WA) from the write address counter 10. That is, the first buffer memory 18 or the second buffer memory 20 receiving a write control signal (W) and the write address signal (WA) stores the input data (INPUT) at the designated memory cell dictated by the write address signal (WA). The write address signal WA determines the memory cell location to store the input data (INPUT).
The first and second buffer memories 18 and 20 output the stored input data (INPUT) to an interpolation filter 24 in accordance with the read address signal (RA) from the read address counter 16 and the read control signal (R) from the memory controller 14. That is, the first buffer memory 18 or the second buffer memory 20 receiving the read control signal (R) and the read address signal (RA) outputs the stored input data (INPUT) from the memory cell location dictated by the read address signal (RA).
The interpolation controller 22 stores filter coefficient values, used by the interpolation filter 24, and controls a linear interpolation process in the interpolation filter 24 based on the count value from the master counter 12. The interpolation filter 24 linearly interpolates the stored input data (INPUT) outputted from the first and second buffer memories 18 or 20 in accordance with the output from the interpolation controller 22 to convert the input data (INPUT) sampled at a frequency (f.sub.A) into output data (OUTPUT) compatible with a sampling frequency (f.sub.B) based on the filter coefficient values stored in the interpolation controller 22.
The operation of the prior art frequency converter, as shown in FIG. 1, will now be described.
The write address counter 10 outputs the write address signal (WA) based on the sampling pulse signal (S.sub.A) having the sampling frequency (f.sub.A) and the clear signal (CLEAR) from the memory controller 14. The sampling frequency (f.sub.A) corresponds to the sampling rate of the input data (INPUT). Thus, the write address counter 10 outputs the write address signal (WA) at the sampling frequency (f.sub.A). As a result, the write address counter 10 outputs the write address signal (WA) to store the input data (INPUT) in either the first buffer memory 18 or the second buffer memory 20 at the same time the input data (INPUT) is sampled.
The memory controller 14 clears the write address counter 10 and the read address counter 16 by outputting the clear signal (CLEAR). Specifically, when the sampling frequencies (f.sub.A, f.sub.B) have a predetermined ratio (M:N), the memory controller 14 outputs the clear signal (CLEAR) to the write address counter 10 at every M number of clock pulses of the frequency (f.sub.A) and outputs the clear signal (CLEAR) to the read address counter 16 at every N number of the clock pulses of the frequency (f.sub.B). Furthermore, because for a given period of M pulses of the sampling pulse signal (S.sub.A) there will be N pulses of the sampling pulse signal (S.sub.B) for that period, M number of input data (INPUT) will be stored and N number of the stored input data (INPUT) will be outputted for that period.
The memory controller 14 also outputs the clear signal (CLEAR) to the master counter 12. The master counter 12 outputs a count value based on the number of pulses of the sampling pulse signal (S.sub.B) prior to receiving the clear signal (CLEAR). That is, after receiving a clear signal (CLEAR) the count value is cleared. The count value from the master counter 12 is outputted to the memory controller 14 and the interpolation controller 22.
In accordance with the write address signal (WA) and the write control signal (W), the input data (INPUT) is alternately stored in the first and second buffer memories 18 and 20. At the same time, the stored input data (INPUT) is alternately outputted from the first and second buffer memories 18 and 20 in accordance with the read address signal (RA) and the read control signal (R). That is, while the first buffer memory 18 stores input data (INPUT) synchronized with the sampling frequency (f.sub.A), the second buffer memory 20 outputs its stored input data (INPUT) in accordance with read address signal (RA) synchronized with the sampling frequency (f.sub.B). Specifically, the memory controller 14 outputs a write control signal (W) to the buffer memory 18 to store input data (INPUT) in accordance with the received write address signal (WA). At the same time, the memory controller 14 outputs a read control signal (R) to the second buffer memory 20 to output a stored input data (INPUT) in accordance with the received read address signal (RA). Likewise, storing of the input data (INPUT) into the second buffer memory 20 while reading the stored input data (INPUT) from the first buffer memory 18 is performed in the same manner as above with exception of the (W) control signal being applied to the second buffer memory 20 and a read control signal (R) being applied to the first buffer memory 18.
Alternately outputting of stored input data (INPUT) is performed in the same manner as alternately storing the input data (INPUT) except the read control signal (R) and the read address signal (RA) are applied to a different buffer memory than a buffer memory receiving the write control signal (W) and the write address signal (WA).
As described above, the first and second buffer memories 18 and 20, respectively, alternately perform a write operation in accordance with the sampling frequency (f.sub.A) and a read operation in accordance with the sampling frequency (f.sub.B).
Accordingly, the interpolation filter :24 receives the stored input data (INPUT) from the first and second buffer memories 18 and 20 and generates output data (OUTPUT) using filter coefficient values stored in the interpolation controller 22. The interpolation filter 24 performs a linear interpolation operation explained by U.S. Pat. No. 4,630,034 to generate the output data (OUTPUT). The linear interpolation operation uses the filter coefficient values, stored in the interpolation controller 22, to convert the input data (INPUT) sampled at the frequency (f.sub.A) into output data (OUTPUT) compatible at the frequency (f.sub.B).
However, in the above-described prior art frequency converter process, a pair of buffer memories 18 and 20 are employed to handle the sampled data, which increases the amount of memory used and requires a complicated memory control circuit to control the alternating storage of data therein and to control the alternating access thereof. Further, a read only memory ROM is required to store the filter coefficient values, which results in increased hardware costs. Plus, in general, processing speed has improved to a degree in that reading coefficient values from a look-up table, i.e., a ROM memory, is no longer faster than performing a discrete calculation to obtain the coefficient values, in some circumstances.